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2.5 VOLT HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40, 131,072 x 40
IDT72T4088, IDT72T4098 IDT72T40108, IDT72T40118
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FEATURES
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Choose among the following memory organizations: IDT72T4088 16,384 x 40 IDT72T4098 32,768 x 40 IDT72T40108 65,536 x 40 IDT72T40118 131,072 x 40 Up to 250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR User selectable HSTL or LVTTL I/Os Read Enable & Read Clock Echo outputs aid high speed operation 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage 3.3V Input tolerant Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input enables/disables Write Operations Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag
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can default to one of four preselected offsets Dedicated serial clock input for serial programming of flag offsets User selectable input and output port bus sizing -x40 in to x40 out -x40 in to x20 out -x40 in to x10 out -x20 in to x40 out -x10 in to x40 out Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty and Full flags signal FIFO status Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into High-Impedance state JTAG port, provided for Boundary Scan function 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) High-performance submicron CMOS technology Industrial temperature range (-40C to +85C) is available
FUNCTIONAL BLOCK DIAGRAM
D0 -Dn (x40, x20, x10)
WEN WCS WCLK SREN SEN SCLK WSDR
INPUT REGISTER
OFFSET REGISTER
SI SO FF/IR PAF EF/OR PAE FWFT FSEL0 FSEL1
WRITE CONTROL LOGIC RAM ARRAY 16,384 x 40, 32,768 x 40 65,536 x 40 131,072 x 40
FLAG LOGIC
WRITE POINTER
READ POINTER
BM IW OW MRS PRS TCK TRST TMS TDO TDI Vref HSTL
BUS CONFIGURATION RESET LOGIC OUTPUT REGISTER
READ CONTROL LOGIC
RT MARK RSDR
JTAG CONTROL (BOUNDARY SCAN)
RCLK REN RCS
HSTL I/0 CONTROL
OE
EREN
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Q0 -Qn (x40, x20, x10)
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.
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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DECEMBER 2003
DSC-5995/8
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
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PIN CONFIGURATIONS
A1 BALL PAD CORNER
A
VCC VCC D38 D1 D4 D7 D9 GND GND Q1 Q3 Q5 Q7 Q9 VDDQ VDDQ
B
D35 D36 D39 D2 D5 D8 HSTL GND GND Q0 Q2 Q4 Q6 Q8 Q22 Q23
C
D34 D37 D0 D3 D6 VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q20 Q21 Q24
D
D33 D32 D31 VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q27 Q26 Q25
E
D30 TDI TRST GND VDDQ MARK Q29 Q28
F
TCK TMS TDO VDDQ VDDQ RCS RT REN
G
WCLK FWFT PAF VDDQ GND GND GND GND GND VDDQ OE RCLK
H
WEN WCS FF/IR VDDQ GND GND GND GND GND VDDQ SCLK SI
J
MRS FSEL1 FSEL0 GND GND GND GND GND GND VDDQ SEN SREN
K
IW BM PRS VCC GND GND GND GND GND VDDQ SO EREN
L
WSDR RSDR OW VCC GND VDDQ PAE ERCLK
M
D27 D28 D29 VCC VDDQ EF/OR Q30 Q31
N
D23 D20 D26 VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q32 Q33 Q34
P
D24 D21 D18 GND VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ Q35 Q36 Q37
R
D25 D22 D19 D16 D14 D12 D10 GND GND Q19 Q17 Q15 Q13 Q11 Q38 Q39
T
VCC VCC VREF D17 D15 D13 D11 GND GND Q18 Q16 Q14 Q12 Q10 VDDQ VDDQ
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PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB) TOP VIEW
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
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DESCRIPTION
The IDT72T4088/72T4098/72T40108/72T40118 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability to read and write data on both rising and falling edges of clock. The device has a flexible x40/x20/x10 Bus-Matching mode and the option to select single or double data rates for input and output ports. These FIFOs offer several key user benefits: * Flexible x40/x20/x10 Bus-Matching on both read and write ports * Ability to read and write on both rising and falling edges of a clock * User selectable Single or Double Data Rate of input and output ports * A user selectable MARK location for retransmit * User selectable I/O structure for HSTL or LVTTL * The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. * High density offerings up to 5Mbit * High speed operation of up to 250MHz Bus-Matching Double Data Rate FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that require fast data transfer on both rising and falling edges of the clock. This is a great alternative to increasing data rate without extending the width of the bus or the speed of the device. They are also effective in applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 40-bit, 20-bit, or a 10-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs can be written into the FIFO on every rising and falling edge of WCLK when WEN is asserted and Write Single Data Rate (WSDR) pin held HIGH. Data can be selected to write only on the rising edges of WCLK if WSDR is asserted. To guarantee functionality of the device, WEN must be a controlled signal and not tied to ground. This is important because WEN must be HIGH during the time when the Master Reset (MRS) pulse is LOW. In addition, the WSDR pin must be tied HIGH or LOW. It is not a controlled signal and cannot be changed during FIFO operation. Write operations can be selected for either Single or Double Data Rate mode. For Single Data Rate operation, writing into the FIFO requires the Write Single Data Rate (WSDR) pin to be asserted. Data will be written into the FIFO on the rising edge of WCLK when the Write Enable (WEN) is asserted. For Double Data Rate operations, writing into the FIFO requires WSDR to be deasserted. Data will be written into the FIFO on both rising and falling edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and a Read Enable (REN) input. Data is read from the FIFO on every rising and falling edge of RCLK when REN is asserted and Read Single Data Rate (RSDR) pin held HIGH. Data can be selected to read only on the rising edges of RCLK if RSDR is asserted. To guarantee functionality of the device, REN must be a controlled signal and not tied to ground. This is important because REN must be HIGH during the time when the Master Reset (MRS) pulse is LOW. In addition, the RSDR pin must be tied HIGH or LOW. It is not a controlled signal and cannot be changed during FIFO operation. Read operations can be selected for either Single or Double Data Rate mode. Similar to the write operations, reading from the FIFO in single data rate requires the Read Single Data Rate (RSDR) pin to be asserted. Data will be read from the FIFO on the rising edge of RCLK when the Read Enable (REN) is asserted. For Double Data Rate operations, reading into the FIFO requires RSDR to be
deasserted. Data will be read out of the FIFO on both rising and falling edge of RCLK when and REN is asserted. Both the input and output port can be selected for either 2.5V LVTTL or HSTL operation. This can be achieved by tying the HSTL signal LOW for LVTTL or HIGH for HSTL voltage operation. When the read port is setup for HSTL mode, the Read Chip Select (RCS) input also has the benefit of disabling the read port inputs, providing additional power savings. There is the option of selecting different data rates on the input and output ports of the device. There are a total of four combinations to choose from, Double Data Rate to Double Data Rate (DDR to DDR), DDR to Single Data Rate (DDR to SDR), SDR to DDR, and SDR to SDR. The rates can be set up using the WSDR and RSDR pins. For example, to set up the input to output combination of DDR to SDR, WSDR will be HIGH and RSDR will be LOW. Read and write operations are initiated on the rising edge of RCLK and WCLK respectively, never on the falling edge. If REN or WEN is asserted after a rising edge of clock, no read or write operations will be possible on the falling edge of that same pulse. An Output Enable (OE) input is provided for high-impedance control of the outputs. A read Chip Select (RCS) input is also provided for synchronous enable/disable of the read port control input, REN. The RCS input is synchronized to the read clock, and also provides high-impedance controls to the Qn data outputs. When RCS is disabled, REN will be disabled internally and the data outputs will be in High-Impedance. Unlike the Read Chip Select signal however, OE is not synchronous to RCLK. Outputs are high-impedanced shortly after a delay time when the OE transitions from LOW to HIGH. The Echo Read Enable (EREN) and Echo Read Clock (ERCLK) outputs are used to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. These output signals from the read port are required for high-speed data communications. Data read from the read port is available on the output bus with respect to EREN and ERCLK, which is useful when data is being read at high-speed operations where synchronization is important. The frequencies of both the RCLK and WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of one clock input with respect to another. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. Be aware that in Double Data Rate (DDR) mode only the IDT Standard mode is available. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of RCLK. A read operation does not have to be performed to access the first word written to the FIFO. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have four flag pins, EF/OR (Empty Flag or Output Ready), FF/ IR (Full Flag or Input Ready), PAE (Programmable Almost-Empty flag), and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. PAE and PAF are always available for use, irrespective of timing mode.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
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DESCRIPTION (CONTINUED)
PAE and PAF flags can be programmed independently to switch at any point in memory. Programmable offsets mark the location within the internal memory that activates the PAE and PAF flags and can only be programmed serially. To program the offsets, set SEN active and data can be loaded via the Serial Input (SI) pin at the rising edge of SCLK. To read out the offset registers serially, set SREN active and data can be read out via the Serial Output (SO) pin at the rising edge of SCLK. Four default offset settings are also provided, so that PAE can be marked at a predefined number of locations from the empty boundary and the PAF threshold can also be marked at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0 and FSEL1 pins. During Master Reset (MRS), the following events occur: the read and write pointers are set to the first location of the internal FIFO memory, the FWFT pin selects IDT Standard mode or FWFT mode, the bus width configuration of the read and write port is determined by the state of IW and OW, and the default offset values for the programmable flags are set. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode and the values stored in the programmable offset registers before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. The timing of the PAE and PAF flags are synchronous to RCLK and WCLK, respectively. The PAE flag is asserted upon the rising edge of RCLK only and
not WCLK. Similarly the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. This device includes a Retransmit from Mark feature that utilizes two control inputs, MARK and RT (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at the point will be marked. Any subsequent retransmit operation (when RT goes LOW), will reset the read pointer to this "marked" location. The device can be configured with different input and output bus widths as previously stated. These rates are: x40 to x40, x40 to x20,x40 to x10, x20 to x40, and x10 to x40. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. A JTAG test port is provided, here the FIFO has fully functional boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. The Double Data Rate FIFO has the capability of operating in either LVTTL or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both input and output ports will operate in either HSTL or LVTTL mode, but cannot be selected independent of one another. The IDT72T4088/72T4098/72T40108/72T40118 are fabricated using IDT's high-speed submicron CMOS technology.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
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PARTIAL RESET (PRS) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) WRITE CHIP SELECT (WCS) WRITE SINGLE DATA RATE (WSDR) (x40, x20, x10) DATA IN (D0 - Dn) SERIAL CLOCK (SCLK) SERIAL ENABLE(SEN) SERIAL READ ENABLE(SREN) FIRST WORD FALL THROUGH (FWFT) SERIAL INPUT (SI) SERIAL OUTPUT (SO) FULL FLAG/INPUT READY (FF/IR) PROGRAMMABLE ALMOST-FULL (PAF)
MASTER RESET (MRS) READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE)
IDT 72T4088 72T4098 72T40108 72T40118
READ CHIP SELECT (RCS) READ SINGLE DATA RATE (RSDR) (x40, x20, x10) DATA OUT (Q0 - Qn) RCLK ECHO (ERCLK) REN ECHO (EREN) MARK RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE)
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INPUT WIDTH (IW)
OUTPUT WIDTH (OW)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 -- BUS-MATCHING CONFIGURATION MODES
BM L H H H H
NOTE: 1. Pin status during Master Reset.
IW L L L H H
OW L L H L H
Write Port Width x40 x40 x40 x20 x10
Read Port Width x40 x20 x10 x40 x40
TABLE 2 -- DATA RATE-MATCHING CONFIGURATION MODES
WSDR H H L L RSDR H L H L Write Port Width Double Data Rate Double Data Rate Single Data Rate Single Data Rate Read Port Width Double Data Rate Single Data Rate Double Data Rate Single Data Rate
NOTE: 1. Pin status during Master Reset. 2. Data Rate Matching can be used in conjunction with Bus-Matching modes.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
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PIN DESCRIPTION
Symbol & Pin No. BM(1) (K2) Name Bus-Matching I/O TYPE LVTTL INPUT Description During Master Reset, this pin along with IW and OW selects the bus sizes for both write and read ports.
Data Inputs D0-D39 (See Pin No. table for details) EF/OR (M14) ERCLK (L16) EREN (K16) FF/IR (H3) FSEL0(1) (J3) FSEL1(1) (J2) FWFT (G2) HSTL(1) (B7) IW(1) (K1) MARK (E14) MRS (J1) OE (G15) OW(1) (L3) PAE (L15) PAF (G3) PRS (K3) Empty Flag/ Output Ready Echo Read Clock Echo Read Enable Full Flag/ Input Ready Flag Select Bit 0 Flag Select Bit 1 First Word Fall Through HSTL Select Input Width Mark Read Pointer for Retransmit Master Reset
HSTL-LVTTL Data inputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused input pins are in a don't INPUT care state. The data bus is sampled on both rising and falling edges of WCLK when WEN is enabled and DDR Mode is enabled or on the rising edges of WCLK only in SDR Mode. HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory OUTPUT is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. HSTL-LVTTL Read Clock Echo output, must be equal to or faster than the Qn data outputs. OUTPUT HSTL-LVTTL Read Enable Echo output, used in conjunction with ERCLK. OUTPUT HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is OUTPUT empty. In FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. LVTTL INPUT LVTTL INPUT LVTTL INPUT LVTTL INPUT LVTTL INPUT During Master Reset, this input along with FSEL1 will select the default offset values for the programmable flags PAE and PAF. There are four possible settings available. During Master Reset, this input along with FSEL0 will select the default offset values for the programmable flags PAE and PAF. There are four possible settings available. During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in DDR mode. In SDR mode, the first word will always fall through on the rising edge. This input pin is used to select HSTL or 2.5V LVTTL device operation. If HSTL inputs are required, this input must be tied HIGH, otherwise it must be tied LOW and cannot toggle during operation. During Master Reset, this pin along with OW and BM, selects the bus width of the read and write port.
HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit INPUT operation will reset the read pointer to this position. There is an unlimited number to times to set the mark location, but only the most recent location marked will be acknowledged. HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Master INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, and programmable flag default settings. HSTL-LVTTL When HIGH, data outputs Q0-Q39 are in high impedance. When LOW, the data outputs Q0-Q39 are enabled. INPUT No other outputs are affected by OE. LVTTL INPUT During Master Reset, this pin along with IW and BM, selects the bus width of the read and write port.
Output Enable Output Width Programmable Almost-Empty Flag
HSTL-LVTTL PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n, which is OUTPUT stored in the Empty Offset register. PAE goes LOW if the number of words in the FIFO memory is less than offset n.
Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored Almost-Full Flag OUTPUT in the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m. Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Partial INPUT Reset, the existing mode (IDT standard or FWFT) and programmable flag settings are not affected. HSTL-LVTTL Data outputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused output pins should not OUTPUT be connected. The output data is clocked on both rising and falling edges of RCLK when REN is enabled and DDR Mode is enabled or on the rising edges of RCLK only in SDR Mode. HSTL-LVTTL Input clock when used in conjunction with REN for reading data from the FIFO memory and output register. INPUT
Q0-Q39 Data Outputs (See Pin No. table for details) RCLK (G16) Read Clock
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol & Pin No. RCS (F14) Name I/O TYPE Description Read Chip Select HSTL-LVTTL RCS provides synchronous enable/disable control of the read port and High-Impedance control of the INPUT Qn data outputs, synchronous to RCLK. When using RCS the OE pin must be tied LOW. During Master or Partial Reset the RCS input is don't care, if OE is LOW the data outputs will be Low-Impedance regardless of RCS. Read Enable HSTL-LVTTL When LOW and in DDR mode, REN along with a rising and falling edge of RCLK will send data in FIFO INPUT memory to the output register and read the current data in output register. In SDR mode data will only be read on the rising edge of RCLK only. LVTTL INPUT When LOW, this input pin sets the read port to Single Data Clock mode. When HIGH, the read port will operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during operation.
REN (F16) RSDR(1) (L2) RT (F15)
Read Single Data Rate Retransmit
HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the read pointer to the first location in memory. EF flag INPUT is set to LOW (OR to HIGH in FWFT mode). The write pointer, offset registers, and flag settings are not affected. If a mark has been set via the MARK input pin, then the read pointer will initialize to the mark location when RT is asserted. LVTTL INPUT A rising edge of SCLK will clock the serial data present on the SI input into the offset registers provided that SEN is enabled. A rising edge of SCLK will also read data out of the offset registers provided that SREN is enabled.
SCLK (H15) SEN (J15) SREN (J16) SI (H16) SO (K15) TCK(2) (F1)
Serial Clock
Serial Input Enable Serial Read Enable Serial Input Serial Output JTAG Clock
HSTL-LVTTL SEN used in conjunction with SI and SCLK enables serial loading of the programmable flag offsets. INPUT HSTL-LVTTL SREN used in conjunction with SO and SCLK enables serial reading of the programmable flag offsets. INPUT HSTL-LVTTL This input pin is used to load serial data into the programmable flag offsets. Used in conjunction with SEN INPUT and SCLK. HSTL-LVTTL This output pin is used to read data from the programmable flag offsets. Used in conjunction with SREN OUTPUT and SCLK. HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFTDR and SHIFT-IR controller states. HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not INPUT automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in highimpedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected. HSTL-LVTTL Input clock when used in conjunction with WEN for writing data into the FIFO memory. INPUT
TDI(2) (E2) TDO(2) (F3)
JTAG Test Data Input JTAG Test Data Output
TMS(2) (F2) TRST(2) (E3)
JTAG Mode Select JTAG Reset
WCLK (G1) WCS (H2) WEN (H1)
Write Clock
Write Chip Select HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations. INPUT Write Enable HSTL-LVTTL When LOW and in DDR mode, WEN along with a rising and falling edge of WCLK will write data into the INPUT FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol & Pin No. WSDR(1) (L1) VCC (See below) VDDQ (See below) GND (See below) Vref (T3) Name Write Single Data Rate +2.5V Supply O/P Rail Voltage Core Ground Pin Reference Voltage I/O TYPE LVTTL INPUT INPUT INPUT INPUT INPUT Description When LOW, this input pin sets the write port to Single Data Clock mode. When HIGH, the write port will operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle during operation. There are Vcc supply inputs and must be connected to the 2.5V supply rail. This pin should be tied to the desired voltage rail for providing power to the output drivers. Nominally 1.5V or 1.8V for HSTL, 2.5V for LVTTL. These are Ground pins are for the core device and must be connected to the GND rail. This is a Voltage Reference input and must be connected to a voltage level determined in the Recommended DC Operating Conditions section. This provides the reference voltage when using HSTL class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 25-28 and Figures 5-7.
PIN NUMBER TABLE
Symbol D0-39 Name Data Inputs I/O TYPE Pin Number HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7, INPUT D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3, D20-N2, D21-P2, D22-R2, D23-N1, D24-P1, D25-R1, D26-N3, D(27-29)-M(1-3), D30-E1, D(31-33)-D(3-1), D34-C1, D(35,36)-B(1,2), D37-C2, D38-A3, D39-B3 HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14 OUTPUT Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10, Q(20,21)-C(14,15), Q(22,23)-B(15,16), Q24-C16, Q(25-27)-D(16-14), Q(28,29)-E(16,15), Q(30,31)-M(15,16), Q(32-34)- N(14-16), Q(35-37)-P(14-16), Q(38,39)-R(15,16) INPUT INPUT INPUT A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2) A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13), P(10-13), T(15,16) A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9), P(4,8,9), R(8,9), T(8,9)
Q0-39
Data Outputs
VCC VDDQ GND
+2.5V Supply O/P Rail Voltage Ground Pin
8
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TSTG IOUT Rating Terminal Voltage with respect to GND Storage Temperature DC Output Current Commercial -0.5 to +3.6(2) -55 to +125 -50 to +50 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN(2,3) COUT(1,2) Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10(3) 10 Unit pF pF
C
mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Compliant with JEDEC JESD8-5. VCC terminal only.
NOTES: 1. With output deselected, (OE VIH). 2. Characterized values, not currently tested. 3. CIN for Vref is 20pF.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH Supply Voltage Supply Voltage Input High Voltage LVTTL eHSTL HSTL LVTTL eHSTL HSTL eHSTL HSTL Parameter Min. 2.375 0 1.7 VREF+0.2 VREF+0.2 -0.3 -- -- 0.8 0.68 0 -40 Typ. 2.5 0 -- -- -- -- -- -- 0.9 0.75 -- -- Max. 2.625 0 3.45 -- -- 0.7 VREF-0.2 VREF-0.2 1.0 0.9 70 85 Unit V V V V V V V V V V
VIL
Input Low Voltage
Voltage Reference Input VREF (HSTL only) TA TA
Operating Temperature Commercial Operating Temperature Industrial
C C
NOTE: 1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V 0.125V, TA = 0C to +70C;Industrial: VCC = 2.5V 0.125V, TA = -40C to +85C)
Symbol ILI ILO VOH
(5)
Parameter Input Leakage Current Output Leakage Current Output Logic "1" Voltage, IOH = -8 mA @VDDQ = 2.5V 0.125V (LVTTL) IOH = -8 mA @VDDQ = 1.8V 0.1V (eHSTL) IOH = -8 mA @VDDQ = 1.5V 0.1V (HSTL) IOL = 8 mA @VDDQ = 2.5V 0.125V (LVTTL) IOL = 8 mA @VDDQ = 1.8V 0.1V (eHSTL) IOL = 8 mA @VDDQ = 1.5V 0.1V (HSTL) I/O = LVTTL I/O = HSTL I/O = eHSTL I/O = LVTTL I/O = HSTL I/O = eHSTL
Min. -10 -10 VDDQ -0.4 VDDQ -0.4 VDDQ -0.4 -- -- -- -- -- -- -- -- --
Max. 10 10 -- -- -- 0.4V 0.4V 0.4V 20 60 60 10 50 50
Unit A A V V V V V V mA mA mA mA mA mA
VOL
Output Logic "0" Voltage,
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
ICC2(1)
Standby VCC Current (VCC = 2.5V)
NOTES: 1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH. 2. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 0.6mA x fs, fs = WCLK frequency = RCLK frequency (in MHz) for HSTL or eHSTL I/O ICC1 (mA) = 38mA + (0.7mA x fs), fs = WCLK frequency = RCLK frequency (in MHz) 3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x 2N)/2000 fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching. tA = 25C, CL = capacitive load (pf) 4. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)]. 5. Outputs are not 3.3V tolerant.
9
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 2.5V 5%, TA = 0C to +70C;Industrial: VCC = 2.5V 5%, TA = -40C to +85C)
Commercial IDT72T4088L4 IDT72T4098L4 IDT72T40108L4 IDT72T40118L4 Min. Max. -- 250 -- 150 0.6 3.2 0.6 3.2 4 -- 6.7 -- 1.8 -- 2.8 -- 1.8 -- 2.8 -- 1.2 -- 0.5 -- 1.2 -- 0.5 -- 1.2 -- 0.5 -- -- 10 100 -- 45 -- 45 -- 15 -- 5 -- 5 -- 5 -- 30 -- 15 -- 4 -- 10 -- -- 10 0 -- -- 3.2 -- 3.2 -- 3.2 -- 3.2 -- 3.2 -- 3.2 -- 3.6 -- 3.2 -- 3.2 -- 3.2 3.5 -- 3.5 -- 4 -- Commercial IDT72T4088L5 IDT72T4098L5 IDT72T40108L5 IDT72T40118L5 Min. Max. -- 200 -- 150 0.6 3.6 0.6 3.6 5 -- 6.7 -- 2.3 -- 2.8 -- 2.3 -- 2.8 -- 1.5 -- 0.5 -- 1.5 -- 0.5 -- 1.5 -- 0.5 -- -- 10 100 -- 45 -- 45 -- 15 -- 5 -- 5 -- 5 -- 30 -- 15 -- 4 -- 10 -- -- 12 0 -- -- 3.6 -- 3.6 -- 3.6 -- 3.6 -- 3.6 -- 3.6 -- 4 -- 3.6 -- 3.6 -- 3.6 4 -- 4 -- 5 -- Com'l & Ind'l(2) Commercial IDT72T4088L6-7 IDT72T4088L10 IDT72T4098L6-7 IDT72T4098L10 IDT72T40108L6-7 IDT72T40108L10 IDT72T40118L6-7 IDT72T40118L10 Min. Max. Min. Max. Unit -- 150 -- 100 MHz -- 150 -- 100 MHz 0.6 3.8 0.6 4.5 ns 0.6 3.8 0.6 4.5 ns 6.7 -- 10 -- ns 6.7 -- 10 -- ns 2.8 -- 4.5 -- ns 2.8 -- 4.5 -- ns 2.8 -- 4.5 -- ns 2.8 -- 4.5 -- ns 2.0 -- 3.0 -- ns 0.5 -- 0.5 -- ns 2.0 -- 3.0 -- ns 0.5 -- 0.5 -- ns 2.0 -- 3.0 -- ns 0.5 -- 0.5 -- ns -- 10 -- 10 MHz 100 -- 100 -- ns 45 -- 45 -- ns 45 -- 45 -- ns 15 -- 15 -- ns 5 -- 5 -- ns 5 -- 5 -- ns 5 -- 5 -- ns 30 -- 30 -- ns 15 -- 15 -- ns 4 -- 4 -- s 10 -- 10 -- ns -- 15 -- 15 ns 0 -- 0 -- ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns -- 4.3 -- 5 ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns -- 3.8 -- 4.5 ns 5 -- 7 -- ns 5 -- 7 -- ns 6 -- 8 -- ns
Symbol fS1 fS2 tA tASO tCLK1 tCLK2 tCLKH1 tCLKH2 tCLKL1 tCLKL2 tDS tDH tENS tENH tWCSS tWCSH fC tSCLK tSCKH tSCKL tSDS tSDH tSENS tSENH tRS tRSS tHRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAFS tPAES tERCLK tCLKEN tRCSLZ tRCSHZ tSKEW1 tSKEW2 tSKEW3
Parameter Clock Cycle Frequency SDR Clock Cycle Frequency DDR Data Access Time Data Access Serial Output Time Clock Cycle Time SDR Clock Cycle Time DDR Clock High Time SDR Clock High Time DDR Clock Low Time SDR Clock Low Time DDR Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time WCS setup time WCS hold time Clock Cycle Frequency (SCLK) Serial Clock Cycle Serial Clock High Serial Clock Low Serial Data In Setup Serial Data In Hold Serial Enable Setup Serial Enable Hold Reset Pulse Width(3) Reset Setup Time HSTL Reset Setup Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low Z(4) Output Enable to Output Valid Output Enable to Output in High Z(4) Write Clock to FF or IR Read Clock to EF or OR Write Clock to Programmable Almost-Full Flag Read Clock to Programmable Almost-Empty Flag RCLK to Echo RCLK output RCLK to Echo REN output RCLK to Active from High-Z RCLK to High-Z(4) Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK & WCLK for EF/OR & FF/IR in DDR mode
Skew time between RCLK and WCLK for PAE and PAF
NOTES: 1. All AC timings apply to both IDT Standard mode and First Word Fall Through mode. 2. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested.
10
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
HSTL 1.5V AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 0.25 to 1.25V 0.4ns 0.75 VDDQ/2
AC TEST LOADS
VDDQ/2 50 I/O Z0 = 50
5995 drw04
NOTE: 1. VDDQ = 1.5V.
Figure 2a. AC Test Load
EXTENDED HSTL 1.8V AC TEST CONDITIONS
tCD (Typical, ns)
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 0.4 to 1.4V 0.4ns 0.9 VDDQ/2
6 5 4 3 2 1
NOTE: 1. VDDQ = 1.8V.
20 30 50
80 100 Capacitance (pF)
200
5995 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5V LVTTL 2.5V AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels GND to 2.5V 1ns VCC/2 VDDQ/2
NOTE: 1. For LVTTL VCC = VDDQ.
11
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
Output Enable OE VIL Output Disable VIH
tOE & tOLZ Output VCC Normally 2 LOW
tOHZ VCC 2 VOL
100mV 100mV
Output Normally VCC HIGH 2
NOTES: 1. REN is HIGH. 2. RCS is LOW.
100mV 100mV
VOH VCC 2
5995 drw04b
READ CHIP SELECT ENABLE & DISABLE TIMING
RCS tENS RCLK tRCSLZ Output VCC Normally 2 LOW tRCSHZ VCC 2 VOL tENH VIH VIL
100mV 100mV
Output Normally VCC HIGH 2
100mV 100mV
VOH VCC 2
5995 drw04c
NOTES: 1. REN is HIGH. 2. OE is LOW.
12
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72T4088/72T4098/72T40108/72T40118 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT input. During Master Reset, if the FWFT pin is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If the FWFT pin is HIGH during Master Reset, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, applying REN = LOW is not necessary. However, subsequent words must be accessed using the Read Enable (REN) and RCLK. Various signals, in both inputs and outputs operate differently depending on which timing mode is in effect. IDT STANDARD MODE In this mode, the status flags FF, PAF, PAE, and EF operate in the manner outlined in Table 4. To write data into the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are listed in Table 3. This parameter is also user programmable. See section on Programmable Flag Offset Loading. Continuing to write data into the FIFO without performing read operations will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (16,384-m) writes for the IDT72T4088, (32,768-m) writes for the IDT72T4098, (65,536-m) writes for the IDT72T40108 and (131,072-m) writes for the IDT72T40118. The offset "m" is the full offset value. The default setting for these values are listed in Table 3. This parameter is also user programmable. See the section on Programmable Flag Offset Loading. When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 16,384 writes for the IDT72T4088, 32,768 writes for the IDT72T4098, 65,536 writes for the IDT72T40108 and 131,072 writes for the IDT72T40118, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF to go HIGH at the conditions described in Table 4 If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. Then the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in IDT Standard mode, the EF and FF outputs are double register-buffered outputs. IDT Standard mode is available when the device is configured in both Single Data Rate and Double Data Rate mode. Relevant timing diagrams for IDT Standard mode can be found in Figure 10, 11, 12, 13, 14, 15, 16, 17, 18 and 23. FIRST WORD FALL THROUGH MODE (FWFT) In this mode, the status flags OR, IR, PAE, and PAF operate in the manner outlined in Table 5. To write data into to the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are listed in Table 3. This parameter is also user programmable. See section on Programmable Flag Offset Loading. Continuing to write data into the FIFO without performing read operations will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (16,385-m) writes for the IDT72T4088, (32,769-m) writes for the IDT72T4098, (65,537-m) writes for the IDT72T40108 and (131,073-m) writes for the IDT72T40118. The offset "m" is the full offset value. The default setting for these values are listed in Table 3. This parameter is also user programmable. See the section on Programmable Flag Offset Loading. When the FIFO is full, the Input Ready (IR) will go LOW, inhibiting further write operations. If no reads are performed after a reset, IR will go LOW after D writes to the FIFO. D = 16,385 writes for the IDT72T4088, 32,769 writes for the IDT72T4098, 65,537 writes for the IDT72T40108 and 131,073 writes for the IDT72T40118, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. If the FIFO is full, the first read operation will cause IR to go HIGH. Subsequent read operations will cause PAF to go HIGH at the conditions described in Table 5. If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. Then the last word has been read from the FIFO, the OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in FWFT mode, the OR flag output is triple register-buffered and the IR flag output is double register-buffered. FWFT mode is only available when the device is configured in Single Data Rate mode. Relevant timing diagrams for IDT Standard mode can be found in Figure 19, 20, 21, 22 and 24.
13
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 3 -- DEFAULT PROGRAMMABLE FLAG OFFSETS
IDT72T4088, 72T4098, 72T40108, 72T40118
FSEL1 H L H L
NOTES: 1. n = empty offset for PAE. 2. m = full offset for PAF.
FSEL0 H H L L
Offsets n,m 255 127 63 7
PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72T4088/ 72T4098/72T40108/72T40118 have internal registers for these offsets. There are four selectable default offset values during Master Reset. These offset values are shown in Table 3. The offset values can also be programmed serially into the FIFO. To load offset values, set SEN LOW and the rising edge of SCLK will
load data from the SI input into the offset registers. SCLK runs at a nominal speed of 10MHz at the maximum. The programming sequence starts with one bit for each SCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. The total number of bits per device is listed in Figure 3, Programmable Flag Offset Programming Sequence. See Figure 25, Loading of Programmable Flag Registers, for the timing diagram for this mode. The PAE and PAF can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Similar to loading offset values, set SREN LOW and the rising edge of SCLK will send data from the offset registers out to the SO output port. When initializing a read to the offset registers, data will be read starting from the first location in the register, regardless of where it was last read. Figure 3, Programmable Flag Offset Programming Sequence, summarizes the control pins and sequence for programming offset registers and reading and writing into the FIFO. The offset registers may be programmed (and reprogrammed) any time after Master Reset. Valid programming ranges are from 0 to D-1.
TABLE 4 STATUS FLAGS FOR IDT STANDARD MODE
IDT72T4088
0
IDT72T4098
0 1 to n
(1)
IDT72T40108
0 1 to n
(1)
IDT72T40118
0 1 to n
(1)
FF
H H H H L
PAF PAE EF
H H H L L L L H H H L H H H H
Number of Words in FIFO
1 to n
(1)
(8,193) to (16,384-(m+1)) (16,384-m) to 16,383 16,384
(16,385) to (32,768-(m+1)) (32,768-m) to 32,767 32,768
(32,769) to (65,536-(m+1)) (65,537) to (131,072-(m+1)) (65,536-m) to 65,535 65,536 (131,072-m) to 131,071 131,072
NOTE: 1. See table 3 for values for n, m.
TABLE 5 STATUS FLAGS FOR FWFT MODE
IDT72T4088
0
IDT72T4098
0 1 to n+1
(1)
IDT72T40108
0 1 to n+1
(1)
IDT72T40118
0 1 to n+1
(1)
IR
L L L L H
PAF PAE OR
H H H L L L L H H H H L L L L
Number of Words in FIFO
1 to n+1
(1)
(8,194) to (16,385-(m+1)) (16,385-m) to 16,384 16,385
(16,386) to (32,769-(m+1)) (32,769-m) to 32,768 32,769
(32,770) to (65,537-(m+1)) (65,538) to (131,073-(m+1)) (65,537-m) to 65,536 65,537 (131,073-m) to 131,072 131,073
5995 drw05
NOTE: 1. See table 3 for values for n, m. 2. FWFT mode available only in Single Data Rate mode.
14
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72T4088 IDT72T4098 IDT72T40108 IDT72T40118 Serial write to registers: In SDR Mode 28 bits for the IDT72T4088 30 bits for the IDT72T4098 32 bits for the IDT72T40108 34 bits for the IDT72T40118 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) Serial read from registers: In SDR Mode 28 bits for the IDT72T4088 30 bits for the IDT72T4098 32 bits for the IDT72T40108 34 bits for the IDT72T40118 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) Serial write to registers: In DDR Mode 26 bits for the IDT72T4088 28 bits for the IDT72T4098 30 bits for the IDT72T40108 32 bits for the IDT 72T40118 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) Serial read from registers: In DDR Mode 26 bits for the IDT72T4088 28 bits for the IDT72T4098 30 bits for the IDT72T40108 32 bits for the IDT72T40118 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB)
WSDR X
RSDR X
WEN 1
REN 1
SEN 0
SREN 1
WCLK X
RCLK X
SCLK
X
X
1
1
1
0
X
X
1 0 1 1 X
1 1 1 0 X
0 0 1 1 1
1 1 0 0 1
X X X X X
X X X X X X X X
X X
X X X X
Write Memory (DDR) Write Memory (SDR) Read Memory (DDR) Read Memory (SDR) No Operation
5995 drw06
X
X
NOTES: 1. The programming sequence applies to both IDT Standard and FWFT modes. 2. When the input or output ports are in DDR mode, the depth is reduced by half but the overall density remains the same. For example, the IDT72T4088 in SDR mode is 16,384 x 40 = 655,360, in DDR mode the configuration becomes 8,192 x 80 = 655,360. In both cases, the total density are the same.
Figure 3. Programmable Flag Offset Programming Sequence
15
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RETRANSMIT FROM MARK OPERATION The Retransmit from Mark feature allows FIFO data to be read repeatedly starting at a user-selected position. The FIFO is first put into retransmit mode that will "mark" a beginning word and also set a pointer that will prevent ongoing FIFO write operations from over-writing retransmit data. The retransmit data can be read repeatedly any number of times from the "marked" position. The FIFO can be taken out of retransmit mode at any time to allow normal device operation. The "mark" position can be selected any number of times, each selection over-writing the previous mark location. In Double Data Rate, data is always marked in pairs. That is, the unit of data read on the rising and falling edge of WCLK. If the data marked was read on the falling edge of RCLK, then the marked data will be the unit of data read from the rising and falling edge of that particular RCLK edge. Refer to Figure 23, Retransmit from Mark in Double Data Rate Mode, for the timing diagram in this mode. Retransmit operation is available in both IDT standard and FWFT modes. During IDT standard mode the FIFO is put into retransmit mode by a Lowto-High transition on RCLK when the MARK input is HIGH and EF is HIGH. The rising RCLK edge marks the data present in the FIFO output register as the first retransmit data. Again, the data is marked in pairs. Thus if the data marked was read on the falling edge of RCLK, the first part of retransmit will read out the data read on the rising edge of RCLK, followed by the data on the falling edge (the marked data). The FIFO remains in retransmit mode until a rising edge on RCLK occurs while MARK is LOW. Once a marked location has been set, a retransmit can be initiated by a rising edge on RCLK while the Retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before bringing RT LOW. The device indicates the start of retransmit setup by setting EF LOW, also preventing reads. When EF goes HIGH, retransmit setup is complete and read operations may begin starting with the first unit of data at the MARK location. Since IDT standard mode is selected, every word read including the first "marked" word following a retransmit setup requires a LOW on REN. Note, write operations may continue as normal during all retransmit functions, however write operations to the "marked" location will be prevented. See Figure
23, Retransmit from Mark in Double Data Rate Mode, for the relevant timing diagram. During FWFT mode the FIFO is put into retransmit mode by a rising RCLK edge when the MARK input is HIGH and OR is LOW. The rising RCLK edge marks the data present in the FIFO output register as the first retransmit data. The data is marked in pairs. The FIFO remains in retransmit mode until a rising RCLK edge occurs while MARK is LOW. Once a marked location has been set, a retransmit can be initiated by a rising RCLK edge while the Retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before bringing RT LOW. The device indicates the start of retransmit setup by setting OR HIGH, preventing read operations. When OR goes LOW, retransmit setup is complete and on the next rising RCLK edge (RT goes HIGH), the contents of the first retransmit location are loaded onto the output register. Since FWFT mode is selected, the first word appears on the outputs regardless of REN, a LOW on REN is not required for the first word. Reading all subsequent words requires a LOW on REN to enable the rising RCLK edge. See Figure 24, Retransmit from Mark (FWFT mode) for the relevant timing diagram. Before a retransmit can be performed, there must be at least 1280 bits (or 160 bytes) of data between the write pointer and mark location. That is, 40 bits x32 for the x40 mode, 20 bits x64 for the x20 mode, and 10 bits x128 for the x10 mode. Also, once the Mark is set, the write pointer will not increment past the marked location, preventing overwrites of retransmit data. HSTL/LVTTL I/O This device supports both LVTTL and HSTL logic levels on the input and output signals. If LVTTL is desired, a LOW on the HSTL pin will set the inputs and outputs to LVTTL mode. If HSTL is desired, a HIGH on the HSTL pin will set the inputs and outputs to HSTL mode. VREF is the input voltage reference used in HSTL mode. Typically a logic HIGH in HSTL would be Vref + 0.2V and a logic LOW would be VREF - 0.2V. Table 6 illustrates which pins are and are not associated with this feature. Note that all "Static Pins" must be tied to Vcc or GND. These pins are LVTTL only and are purely device configuration pins.
TABLE 6 -- I/O CONFIGURATION
HSTL SELECT HIGH = HSTL LOW = LVTTL Write Port Dn (I/P) WCLK (I/P) WEN (I/P) WCS (I/P) Qn (O/P) RCLK (I/P) REN (I/P) RCS (I/P) MARK (I/P) OE (I/P) RT (I/P) Read Port EF/OR (O/P) PAF (O/P) PAE (O/P) FF/IR (O/P) ERCLK (O/P) EREN (O/P) SCLK (I/P) SI (I/P) SO (O/P) MRS (I/P) PRS (I/P) TCK (I/P) TMS (I/P) Signal Pins TRST (I/P) TDI (I/P) TDO (O/P) SEN (I/P) SREN (I/P) STATIC PINS LVTTL ONLY Static Pins IW (I/P) OW (I/P) BM ((I/P) HSTL (I/P) FSEL1 (I/P) FSEL0 (I/P) FWFT (I/P) WSDR (I/P) RSDR (I/P)
16
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SIGNAL DESCRIPTION INPUTS:
DATA IN (D0 - Dn) (D0 - D39) are data inputs for the 40-bit wide data, (D0 - D19) are data inputs for the 20-bit wide data, or (D0 - D9) are data inputs for 10-bit wide data.
CONTROLS:
MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW and PAF will go HIGH. If FWFT is LOW during Master Reset then IDT Standard mode along with EF and FF are selected. EF will go LOW and FF will go HIGH, If FWFT is HIGH, then the First Word Fall Through (FWFT) mode, along with IR and OR are selected. OR will go HIGH and IR will go LOW. All control settings such as OW, IW, BM, WSDR, RSDR, FSEL0 and FSEL1 are defined during the Master Reset cycle. During a Master Reset the output register is initialized to all zeros. A Master Reset is required after power up before a write operation can take place. MRS is asynchronous. See Figure 8, Master Reset Timing, for the relevant timing diagram. PARTIAL RESET (PRS) A Partial Reset is accomplished whenever the PRS input is taken to a LOW state. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array. PAE goes LOW and PAF goes HIGH. Whichever mode was active at the time of Partial Reset will remain active after Partial Reset. If IDT Standard Mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH and IR will go LOW. Following Partial Reset, all values held in the offset registers remain unchanged. The output register is initialized to all zeroes. PRS is asynchronous. Partial Reset is useful for resetting the read and write pointers to zero without affecting the values of the programmable flag offsets and the timing mode of the FIFO. See Figure 9, Partial Reset Timing, for the relevant timing diagram. RETRANSMIT (RT) The Retransmit (RT) input is used in conjunction with the MARK input. Together they provide a means by which data previously read out of the FIFO can be reread any number of times. When the retransmit operation is selected (i.e. after data has been marked), a rising edge on RCLK while RT is LOW will reset the read pointer back to the memory location set by the user via the MARK input. If IDT Standard mode has been selected, the EF flag will go LOW on the rising edge of RCLK that retransmit was initiated (i.e. rising edge of RCLK while RT is LOW). EF will go back to HIGH on the next rising edge of RCLK, which signifies that retransmit setup is complete. The next read operation will access data from the "marked" memory location. Subsequent retransmit operations may be performed, each time the read pointer returning to the "marked" location. See Figure 23, Retransmit from Mark in Double Data Rate Mode (IDT Standard Mode) for the relevant timing diagram.
If FWFT mode has been selected, the OR flag will go HIGH on the rising edge of RCLK that retransmit was initiated. OR will return LOW on the next rising edge of RCLK, which signifies that retransmit setup is complete. Under FWFT mode, the contents in the marked memory location will be loaded onto the output register on the next rising edge of RCLK. To access all subsequent data, a read operation will be required. Subsequent retransmit operations may be performed, each time the read pointer returning to the "marked" location. See Figure 24, Retransmit from Mark (FWFT Mode) for the relevant timing diagram. MARK The MARK input is used to select Retransmit mode of operation. On a rising edge of RCLK while MARK is HIGH will mark the memory location of the data currently present on the output register, in addition placing the device in retransmit mode. Note, there must be a minimum of 1280 bits (or 160 bytes) of data between the write pointer and mark location. That is, 40 bits x32 for the x40 mode, 20 bits x64 for the x20 mode, and 10 bits x128 for the x10 mode. Also, once the MARK is set, the write pointer will not increment past the "marked" location until the MARK is deasserted. This prevents "overwriting" of retransmit data. The MARK input must remain HIGH during the whole period of retransmit mode, a falling edge of RCLK while MARK is LOW will take the device out of retransmit mode and into normal mode. Any number of MARK locations can be set during FIFO operation, only the last marked location taking effect. Once a mark location has been set the write pointer cannot be incremented past this marked location. During retransmit mode write operations to the device may continue without hindrance. FIRST WORD FALL THROUGH (FWFT) During Master Reset, the state of the FWFT input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode. If, at the time of Master Reset, FWFT is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO memory. It also uses the Full Flag function (FF) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the outputs (Qn) to be read. It also uses Input Ready (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, bringing REN LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. Note that FWFT mode can only be used when the device is configured to Single Data Rate (SDR) mode. WRITE CLOCK (WCLK) A write cycle is initiated on the rising and/or falling edge of the WCLK input. If the Write Single Data Rate (WSDR) pin is selected, data will be written only on the rising edge of WCLK, provided that WEN and WCS are LOW. If the WSDR is not selected, data will be written on both the rising and falling edge of WCLK, provided that WEN and WCS are LOW. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF, IR, and PAF flags will not be updated. The write and read clocks can either be independent or coincident.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH, allowing a write to occur. The FF is updated by two WCLK cycles + tSKEW after the RCLK cycle. To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW, allowing a write to occur. The IR flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle. WEN is ignored when the FIFO is full in either IDT Standard mode or FWFT. WRITE SINGLE DATA RATE (WSDR) When the Write Single Data Rate pin is LOW, the write port will be set to Single Data Rate mode. In this mode, all write operations are based only on the rising edge of WCLK, provided that WEN and WCS are LOW. When WSDR is HIGH, the read port will be set to Double Data Rate mode. In this mode, all write operations are based on both the rising and falling edge of WCLK, provided that WEN and WCS are LOW, on the rising edge of WCLK. READ CLOCK (RCLK) A read cycle is initiated on the rising and/or falling edge of the RCLK input. If the Read Single Data Rate (RSDR) pin is selected, data will be read only on the rising edge of RCLK, provided that REN and RCS are LOW. If the RSDR is not selected, data will be read on both the rising and falling edge of WCLK, provided that REN and RCS are LOW, on the rising edge of RCLK. Setup and hold times must be met with respect to the LOW-to-HIGH transition of the RCLK. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/ OR and PAE flags will not be updated. Write and Read Clocks can be independent or coincident. READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In IDT Standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN provided that the Read Chip Select (RCS) is LOW. When the last word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to occur. Both RCS and REN must be active LOW for data to be read out on the rising edge of RCLK. In FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW after the first write. REN and RCS do not need to be asserted LOW for the First Word to fall through to the output register. All subsequent words require that a read operation to be executed using REN and RCS. The LOW-to-HIGH
transition of RCLK after the last word has been read from the FIFO will make Output Ready (OR) go HIGH with a true read (RCLK with REN and RCS LOW), inhibiting further read operations. REN is ignored when the FIFO is empty. READ SINGLE DATA RATE (RSDR) When the Read Single Data Rate pin is LOW, the read port will be set to Single Data Rate mode. In this mode, all read operations are based only on the rising edge of RCLK, provided that REN and RCS are LOW. When RSDR is HIGH, the read port will be set to Double Data Rate mode. In this mode, all read operations are based on both the rising and falling edge of RCLK, provided that REN and RCS are LOW, on the rising edge of RCLK. SERIAL CLOCK (SCLK) The serial clock is used to load and read data in the programmable offset registers. Data from the Serial Input (SI) can be loaded into the offset registers on the rising edge of SCLK provided that SEN is LOW. Data can be read from the offset registers via the Serial Output (SO) on the rising edge of SCLK provided that SREN is LOW. The serial clock can operate at a maximum frequency of 10MHz and its parameters are different than the FIFO system clock. SERIAL ENABLE (SEN) The SEN input is an enable used for serial programming of the programmable offset registers. It is used in conjunction with SI and SCLK when programming the offset registers. When SEN is LOW, data at the Serial In (SI) input can be loaded into the offset register, one bit for each LOW-to-HIGH transition of SCLK. When SEN is HIGH, the offset registers retain the previous settings and no offsets are loaded. SEN functions the same way in both IDT Standard and FWFT modes. SERIAL READ ENABLE (SREN) The SREN output is an enable used for reading the value of the programmable offset registers. It is used in conjunction with SI and SCLK when reading from the offset registers. When SREN is LOW, data can be read out of the offset register from the SO output, one bit for each LOW-to-HIGH transition of SCLK. When SREN is HIGH, the reading of the offset registers will stop. Whenever SREN is activated values in the offset registers are read starting from the first location in the offset registers and not from where the last offset value was read. SREN functions the same way in both IDT Standard and FWFT modes. SERIAL IN (SI) This pin acts as a serial input for loading PAE and PAF offsets into the programmable offset registers. It is used in conjunction with the Serial Clock (SCLK) and the Serial Enable (SEN). Data from this input can be loaded into the offset register, one bit for each LOW-to-HIGH transition of SCLK provided that SEN is LOW. SERIAL OUT (SO) This pin acts as a serial output for reading the values of the PAE and PAF offsets in the programmable offset registers. It is used in conjunction with the Serial Clock (SCLK) and the Serial Enable Output (SREN). Data from the offset register can be read out using this pin, one-bit for each LOW-to-HIGH transition of SCLK provided that SREN is LOW.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OUTPUT ENABLE (OE) When Output Enable is LOW, the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high-impedance state. During Master or Partial Reset the OE is the only input that can place the output data bus into high-impedance. During reset the RCS input can be HIGH or LOW and has no effect on the output data bus. READ CHIP SELECT (RCS) The Read Chip Select input provides synchronous control of the Read output port. When RCS goes LOW, the next rising edge of RCLK causes the Qn outputs to go to the low-impedance state. When RCS goes HIGH, the next RCLK rising edge causes the Qn outputs to return to high-impedance. During a Master or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only input that provides high-impedance control of the Qn outputs. If OE is LOW, the Qn data outputs will be low-impedance regardless of RCS until the first rising edge of RCLK after a reset is complete. Then if RCS is HIGH the data outputs will go to high-impedance. The RCS input does not effect the operation of the flags. For example, when the first word is written to an empty FIFO, the EF will still go from LOW to HIGH based on a rising edge of RCLK, regardless of the state of the RCS input. Also, when operating the FIFO in FWFT mode the first word written to an empty FIFO will still be clocked through to the output register based on RCLK, regardless of the state of RCS. For this reason the user should pay extra attention when a data word is written to an empty FIFO in FWFT mode. If RCS is HIGH when an empty FIFO is written into, the first word will fall through to the output register but will not be available on the Qn outputs because they are in high-impedance. The user must take RCS active LOW to access this first word, placing the output bus in low-impedance. REN must remain HIGH for at least one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and REN LOW will read out the next word. Care must be taken so as not to lose the first word written to an empty FIFO when RCS is HIGH. Refer to Figure 22, RCS and REN Read Operation (FWFT Mode). The RCS pin must also be active (LOW) in order to perform a Retransmit. See Figure 18 for Read Cycle and Read Chip Select Timing (IDT Standard Mode). See Figure 21 for Read Cycle and Read Chip Select Timing (FWFT Mode). WRITE CHIP SELECT (WCS) The WCS disables all Write Port inputs (data only) if it is held HIGH. To perform normal operations on the write port, the WCS must be enabled. HSTL SELECT (HSTL) The inputs that were listed in Table 6 can be setup to be either HSTL or LVTTL. If HSTL is HIGH, then HSTL operation of those signals will be selected. If HSTL is LOW , then LVTTL will be selected. BUS-MATCHING (BM, IW, OW) The pins BM, IW, and OW are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. See Table 1 for control settings. All flags will operate on the word/byte size boundary as defined by the selection of bus width. See Table 7 for Bus-Matching Write to Read Ratio. FLAG SELECT BITS (FSEL0 and FSEL1) These pins will select the four default offset values for the PAE and PAF flags during Master Reset. The four possible settings are listed on Table 3. Note that the status of these inputs should not change after Master Reset.
OUTPUTS:
DATA OUT (Q0-Q39) (Q0 - Q39) are data outputs for 40-bit wide data, (Q0 - Q19) are data outputs for 20-bit wide data, or (Q0 - Q9) are data outputs for 10-bit wide data. FULL FLAG (FF/IR) This is a dual-purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO (D = 16,384 for the IDT72T4088, 32,768 for the IDT72T4098, 65,536 for the IDT72T40108, 131,072 for the IDT72T40118. See Figure 10, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 16,385 for the IDT72T4088, 32,769 for the IDT72T4098, 65,537 for the IDT72T40108, 131,073 for the IDT72T40118). See Figure 19, Write Timing (FWFT Mode), for the relevant timing information. The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. Note, when the device is in Retransmit mode, this flag is a comparison of the write pointer to the "marked" location. This differs from normal mode where this flag is a comparison of the write pointer to the read pointer. EMPTY FLAG (EF/OR) This is a dual-purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. See Figure 12, Read Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for the relevant timing information. In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. See Figure 20, Read Timing (FWFT Mode), for the relevant timing information. EF/OR is synchronous and updated on the rising edge of RCLK. In IDT Standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered output. PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW when the FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF will go LOW after (D - m) words are written to the FIFO. The PAF will go LOW after (16,384-m) writes for the IDT72T4088, (32,768-m) writes for the IDT72T4098, (65,536-m) writes for the IDT72T40108, (131,072-m) writes for the IDT72T40118. The offset "m" is the full offset value. The default setting for this value is listed in Table 3.
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
In FWFT mode, the PAF will go LOW after (16,385-m) writes for the IDT72T4088, (32,769-m) writes for the IDT72T4098, (65,537-m) writes for the IDT72T40108, (131,073-m) writes for the IDT72T40118. where m is the full offset value. The default setting for this value is listed in Table 3. See Figure 29, Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. Note, when the device is in Retransmit mode, this flag is a comparison of the write pointer to the "marked" location. This differs from normal mode where this flag is a comparison of the write pointer to the read pointer. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the FIFO. The offset "n" is the empty offset value. The default setting for this value is stated in the footnote of Table 3. In FWFT mode, the PAE will go LOW when there are n+1 words or less in the FIFO. The default setting for this value is stated in Table 3. See Figure 30, Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. ECHO READ CLOCK (ERCLK) The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via HSTL. The ERCLK is a free-running clock output, it will always follow the RCLK input regardless of REN and RCS. The ERCLK output follows the RCLK input with an associated delay. This delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when variables within the device may cause changes in the data access times. These variations in access time maybe caused by ambient temperature, supply voltage, or device characteristics. The ERCLK output also compensates for any trace length delays between the Qn data outputs and receiving devices inputs. Any variations effecting the data access time will also have a corresponding effect on the ERCLK output produced by the FIFO device, therefore the ERCLK output level transitions should always be at the same position in time relative to the data outputs. Note, that ERCLK is guaranteed by design to be slower than the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data Output Relationship, Figure 27, Echo Read Clock & Read Enable Operation in Double Data Rate Mode and Figure 28, Echo RCLK & Echo REN Operation for timing information. ECHO READ ENABLE (EREN) The Echo Read Enable output is provided in both HSTL and LVTTL mode, selectable via HSTL. The EREN output is provided to be used in conjunction with the ERCLK output and provides the reading device with a more effective scheme for reading data from the Qn output port at high speeds. The EREN output is controlled by internal logic that behaves as follows: The EREN output is active LOW for the RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of RCLK will cause EREN to go active, LOW if both REN and RCS are active, LOW and the FIFO is NOT empty.
RCLK
tERCLK tERCLK
ERCLK
tA
tD
tA
tD
QSLOWEST(3)
5995 drw07
NOTES: 1. REN is LOW. 2. tERCLK > tA, guaranteed by design. 3. Qslowest is the data output with the slowest access time, tA. 4. Time, tD is greater than zero, guaranteed by design. 5. REN = RCS = OE = 0.
Figure 4. Echo Read Clock and Data Output Relationship
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 7 -- BUS-MATCHING WRITE TO READ RATIO
ONE WRITE TO ONE READ (1:1)
x40 DDR Input to x40 DDR Output WSDR H RSDR H Configuration BM L IW L OW L x40 SDR Input to x40 SDR Output WSDR L RSDR L Configuration BM L IW L OW L
DDR Write Clock x40 Data In DDR Read Clock x40 Data Out Positive Edge 1 D[39:0] <= LW1 Positive Edge 1 Q[39:0] <= LW1 Negative Edge 1 D[39:0] <= LW2 Negative Edge 1 Q[39:0] <= LW2
SDR Write Clock x40 Data In SDR Read Clock x40 Data Out Positive Edge 1 D[39:0] <= LW1 Positive Edge 1 Q[39:0] <= LW1
x40 SDR Input to x20 DDR Output WSDR L RSDR H Configuration BM H IW L OW L
x20 DDR Input to x40 SDR Output WSDR H RSDR L Configuration BM H IW H OW L
SDR Write Clock x40 Data In Positive Edge 1 D[39:20] <= W1 D[19:0] <= W2
DDR Read Clock x20 Data Out Positive Edge 1 Q[19:0] <= W1 Negative Edge 1 Q[19:0] <= W2
DDR Write Clock x20 Data In Positive Edge 1 D[19:0] <= W1 Negative Edge 1 D[19:0] <= W2
SDR Read Clock x40 Data Out Positive Edge 1 Q[39:20] <= W1 Q[19:0] <= W2
ONE WRITE TO TWO READ (1:2)
x40 DDR Input to x40 SDR Output WSDR H Configuration RSDR BM L L IW L OW L x40 SDR Input to x20 SDR Output WSDR L Configuration RSDR BM L H IW L OW L
DDR Write Clock x40 Data In Positive Edge 1 D[39:0] <= LW1 Negative Edge 1 D[39:0] <= LW2
SDR Read Clock x40 Data Out Positive Edge 1 Q[39:0] <= LW1 Positive Edge 2 Q[39:0] <= LW1
SDR Write Clock x40 Data In SDR Read Clock x20 Data Out Positive Edge 1 D[39:20] <= LW1 Positive Edge 1 Q[19:0] <= LW1 D[19:0] <= LW2 Positive Edge 2 Q[19:0] <= LW2
x40 DDR Input to x20 DDR Output WSDR H RSDR H Configuration BM H IW L OW L x20 Data Out Q[19:0] <= LW1 Q[19:0] <= LW2 Q[19:0] <= LW3 Q[19:0] <= LW4
21
x40 SDR Input to x10 DDR Output WSDR L RSDR H Configuration BM H IW L OW H x10 Data Out Q[9:0] <= B1 Q[9:0] <= B2 Q[9:0] <= B3 Q[9:0] <= B4
DDR Write Clock x40 Data In Positive Edge 1 D[39:20] <= LW1 D[19:0] <= LW2 Negative Edge 1 D[39:20] <= LW3 D[19:0] <= LW4
DDR Read Clock Positive Edge 1 Negative Edge 1 Positive Edge 2 Negative Edge 2
SDR Write Clock x40 Data In Positive Edge 1 D[39:30] <= B1 D[29:20] <= B2 D[19:10] <= B3 D[9:0] <= B4
DDR Read Clock Positive Edge 1 Negative Edge 1 Positive Edge 2 Negative Edge 2
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 7 -- BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
ONE WRITE TO FOUR READ (1:4)
x40 DDR Input to x20 SDR Output WSDR H RSDR L Configuration BM H IW L OW L x20 Data Out Q[19:0] <= LW1 Q[19:0] <= LW2 Q[19:0] <= LW3 Q[19:0] <= LW4 x40 SDR Input to x10 SDR Output WSDR L RSDR L Configuration BM H IW L OW H x10 Data Out Q[9:0] <= B1 Q[9:0] <= B2 Q[9:0] <= B3 Q[9:0] <= B4
DDR Write Clock x40 Data In Positive Edge 1 D[39:20] <= LW1 D[19:0] <= LW2 Negative Edge 1 D[39:20] <= LW3 D[19:0] <= LW4
SDR Read Clock Positive Edge 1 Positive Edge 2 Positive Edge 3 Positive Edge 4
SDR Write Clock x40 Data In Positive Edge 1 D[39:30] <= B1 D[29:20] <= B2 D[19:10] <= B3 D[9:0] <= B4
SDR Read Clock Positive Edge 1 Positive Edge 2 Positive Edge 3 Positive Edge 4
x40 DDR Input to x10 DDR Output WSDR H RSDR H Configuration BM H IW L OW H x10 Data Out Q[9:0] <= B1 Q[9:0] <= B2 Q[9:0] <= B3 Q[9:0] <= B4 Q[9:0] <= B5 Q[9:0] <= B6 Q[9:0] <= B7 Q[9:0] <= B8
DDR Write Clock x40 Data In Positive Edge 1 D[39:30] <= B1 D[29:20] <= B2 D[19:10] <= B3 D[9:0] <= B4 Negative Edge 1 D[39:30] <= B5 D[29:20] <= B6 D[19:10] <= B7 D[9:0] <= B8
SDR Read Clock Positive Edge 1 Negaitive Edge 1 Positive Edge 2 Negaitive Edge 2 Positive Edge 3 Negaitive Edge 3 Positive Edge 4 Negaitive Edge 4
ONE WRITE TO EIGHT READ (1:8)
x40 DDR Input to x10 SDR Output WSDR H Configuration RSDR BM L H IW L OW H x10 Data Out Q[9:0] <= B1 Q[9:0] <= B2 Q[9:0] <= B3 Q[9:0] <= B4 Q[9:0] <= B5 Q[9:0] <= B6 Q[9:0] <= B7 Q[9:0] <= B8
22
DDR Write Clock x40 Data In Positive Edge 1 D[39:30] <= B1 D[29:20] <= B2 D[19:10] <= B3 D[9:0] <= B4 Negative Edge 1 D[39:30] <= B5 D[29:20] <= B6 D[19:10] <= B7 D[9:0] <= B8
SDR Read Clock Positive Edge 1 Positive Edge 2 Positive Edge 3 Positive Edge 4 Positive Edge 5 Positive Edge 6 Positive Edge 7 Positive Edge 8
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 7 -- BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
TWO WRITE TO ONE READ (2:1)
x40 SDR Input to x40 DDR Output WSDR L RSDR H Configuration BM L IW L OW L x20 DDR Input to x40 DDR Output WSDR H RSDR H Configuration BM H IW H OW L x40 Data Out Q[39:20] <= W1 Q[19:0] <= W2 Q[39:20] <= W3 Q[19:0] <= W4
SDR Write Clock x40 Data In DDR Read Clock x40 Data Out Positive Edge 1 D[39:0] <= LW1 Positive Edge 1 Q[39:0] <= LW1 Positive Edge 2 D[39:0] <= LW2 Negative Edge 1 Q[39:0] <= LW2
DDR Write Clock Positive Edge 1 Negative Edge 1 Positive Edge 2 Negative Edge 2
x20 Data In DDR Read Clock D[19:0] <= W1 Positive Edge 1 D[19:0] <= W2 D[19:0] <= W3 Negative Edge 1 D[19:0] <= W4
x20 SDR Input to x40 SDR Output WSDR L RSDR L Configuration BM H IW H OW L
x10 DDR Input to x40 SDR Output WSDR H Configuration RSDR BM L H IW H OW H x40 Data Out Q[39:30] <= B1 Q[29:20] <= B2 Q[19:10] <= B3 Q[9:0] <= B4
SDR Write Clock x20 Data In Positive Edge 1 D[19:0] <= W1 Positive Edge 2 D[19:0] <= W2
SDR Read Clock x40 Data Out Positive Edge 1 Q[39:20] <= W1 Q[19:0] <= W2
DDR Write Clock Positive Edge 1 Negative Edge 1 Positive Edge 2 Negative Edge 2
x10 Data In SDR Read Clock D[9:0] <= B1 Positive Edge 1 D[9:0] <= B2 D[9:0] <= B3 D[9:0] <= B4
FOUR WRITE TO ONE READ (4:1)
x20 SDR Input to x40 DDR Output WSDR L Configuration RSDR BM H H IW H OW L x40 Data Out Q[39:20] <= W1 Q[19:0] <= W2 Q[39:20] <= W3 Q[19:0] <= W4 x10 DDR Input to x40 DDR Output WSDR H Configuration RSDR BM H H IW H OW H x40 Data Out Q[39:30] <= B1 Q[29:20] <= B2 Q[19:10] <= B3 Q[9:0] <= B4 Q[39:30] <= B5 Q[29:20] <= B6 Q[19:10] <= B7 Q[9:0] <= B8
SDR Write Clock Positive Edge 1 Positive Edge 2 Positive Edge 3 Positive Edge 4
x20 Data In DDR Read Clock D[19:0] <= W1 Positive Edge 1 D[19:0] <= W2 D[19:0] <= W3 Negative Edge 1 D[19:0] <= W4
x10 SDR Input to x40 SDR Output WSDR L Configuration RSDR BM L H IW H OW H x40 Data Out Q[39:30] <= B1 Q[29:20] <= B2 Q[19:10] <= B3 Q[9:0] <= B4
23
DDR Write Clock Positive Edge 1 Negative Edge 1 Positive Edge 2 Negative Edge 2 Positive Edge 3 Negative Edge 3 Positive Edge 4 Negative Edge 4
x10 Data In DDR Read Clock D[9:0] <= B1 Positive Edge 1 D[9:0] <= B2 D[9:0] <= B3 D[9:0] <= B4 D[9:0] <= B5 Negative Edge 2 D[9:0] <= B6 D[9:0] <= B7 D[9:0] <= B8
SDR Write Clock Positive Edge 1 Positive Edge 2 Positive Edge 3 Positive Edge 4
x10 Data In SDR Read Clock D[9:0] <= B1 Positive Edge 1 D[9:0] <= B2 D[9:0] <= B3 D[9:0] <= B4
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 7 -- BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
EIGHT WRITE TO ONE READ (8:1)
x10 SDR Input to x40 DDR Output WSDR L RSDR H Configuration BM H IW H OW H x40 Data Out Q[39:30] <= B1 Q[29:20] <= B2 Q[19:10] <= B3 Q[9:0] <= B4 Q[39:30] <= B5 Q[29:20] <= B6 Q[19:10] <= B7 Q[9:0] <= B8
SDR Write Clock Positive Edge 1 Positive Edge 2 Positive Edge 3 Positive Edge 4 Positive Edge 5 Positive Edge 6 Positive Edge 7 Positive Edge 8
x10 Data In DDR Read Clock D[9:0] <= B1 Positive Edge D[9:0] <= B2 D[9:0] <= B3 D[9:0] <= B4 D[9:0] <= B5 Negative Edge D[9:0] <= B6 D[9:0] <= B7 D[9:0] <= B8
TABLE 8 -- TSKEW MEASUREMENT
Data Port Configuration DDR Input to DDR Output Status Flags EF & PAE FF & PAF DDR Input to SDR Output EF & PAE FF & PAF SDR Input to DDR Output EF & PAE FF & PAF SDR Input to SDR Output EF & PAE FF & PAF TSKEW Measurement Negative Edge WCLK to Positive Edge RCLK Negative Edge RCLK to Positive Edge WCLK Negative Edge WCLK to Positive Edge RCLK Positive Edge RCLK to Positive Edge WCLK Positive Edge WCLK to Positive Edge RCLK Negative Edge RCLK to Positive Edge WCLK Positive Edge WCLK to Positive Edge RCLK Positive Edge RCLK to Positive Edge WCLK
24
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
JTAG TIMING SPECIFICATION
tTCK t4 t1
TCK
t2
t3
TDI/ TMS
tDS
TDO
tDH
TDO
t6
TRST
Notes to diagram: t1 = tTCKLOW t2 = tTCKHIGH t3 = tTCKFALL t4 = tTCKRISE t5 = tRST (reset pulse width) t6 = tRSR (reset recovery)
tDO
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t5
Figure 5. Standard JTAG Timing
JTAG AC ELECTRICAL CHARACTERISTICS
(vcc = 2.5V 5%; Tcase = 0C to +85C)
Parameter Symbol Test Conditions Min. JTAG Clock Input Period tTCK JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery
NOTE: 1. Guaranteed by design.
SYSTEM INTERFACE PARAMETERS
IDT72T4088 IDT72T4098 IDT72T40108 IDT72T40118 Parameter Data Output Data Output Hold Data Input Symbol tDO(1) tDOH(1) tDS tDH trise=3ns tfall=3ns Test Conditions Min. 0
10 10
Max. Units 5(1) 5(1) ns ns ns ns ns ns ns
-
100 40 40 50 50
tTCKHIGH tTCKLOW tTCKRISE tTCKFALL tRST tRSR
Max. Units 20 -
ns ns ns
NOTE: 1. 50pf loading on external output signals.
25
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T4088/72T4098/ 72T40108/72T40118 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices.
* * * *
The Standard JTAG interface consists of four basic elements: Test Access Port (TAP) TAP controller Instruction Register (IR) Data Register Port (DR)
The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). The Figure below shows the standard Boundary-Scan Architecture
DeviceID Reg. Boundary Scan Reg. Bypass Reg.
Mux
TDO TDI
T A
TMS TCLK TRST
P TAP Controller
clkDR, ShiftDR UpdateDR
Instruction Decode clklR, ShiftlR UpdatelR Instruction Register
Control Signals
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Figure 6. Boundary Scan Architecture
TEST ACCESS PORT (TAP) The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO).
26
THE TAP CONTROLLER The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data.
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
Test-Logic Reset 0 1 1 1 SelectIR-Scan 1 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0
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0
Run-Test/ Idle
SelectDR-Scan 0 1 Capture-DR 00 Shift-DR 1
0
Input = TMS
EXit1-DR 00 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
1
0
NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). 3. TAP controller must be reset before normal FIFO operations can begin.
Figure 7. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of the TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the FIFO memory and must be reset after power up of the device. See TRST description for more details on TAP controller reset. Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times. This is the reason why the Test Reset (TRST) pin is optional. Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idles otherwise. Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made. Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state other wise.
27
Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCK. The last two significant bits are always required to be "01". Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is also shifted in to the instruction register. Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made. Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted. Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made. Update-IR In this controller state, the instruction in the instruction register is latched in to the latch bank of the Instruction Register on every falling edge of TCK. This instruction also becomes the current instruction once it is latched. Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCK. Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path.
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at UpdateIR state. The instruction register must contain 4 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits. TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. THE BOUNDARY-SCAN REGISTER The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation. THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T4088/72T4098/72T40108/72T40118, the Part Number field contains the following values: Device IDT72T4088 IDT72T4098 IDT72T40108 IDT72T40118 Part# Field 04A3 04A2 04A1 04A0
JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: * Select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and the selected data register. * Define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. The Instruction Register is a 4 bit field (i.e.IR3, IR2, IR1, IR0) to decode 16 different possible instructions. Instructions are decoded as follows. Hex Value 0x02 0x01 0x03 0x0F Instruction IDCODE SAMPLE/PRELOAD HI-IMPEDANCE BYPASS Function Select Chip Identification data register Select Boundary Scan Register JTAG Select Bypass Register
Table 8. JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). IDCODE The optional IDCODE instruction allows the IC to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 32-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the device identification register does not interfere with the operation of the IC. Also, access to the device identification register should be immediately available, via a TAP data-scan operation, after power-up of the IC or after the TAP has been reset using the optional TRST pin or by otherwise moving to the Test-Logic-Reset state. SAMPLE/PRELOAD The required SAMPLE/PRELOAD instruction allows the IC to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the IC. HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an IC to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs. BYPASS The required BYPASS instruction allows the IC to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC.
31(MSB) 28 27 12 11 1 0(LSB) Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 0X33 1
IDT72T4088/4098/40108/40118 JTAG Device Identification Register
28
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tRS MRS tRSS REN tRSS WEN tRSS FWFT(2) tRSS FSEL0(2), FSEL1 tRSS OW(2), IW, BM tHRSS HSTL(2) tRSS WSDR
(2)
tRSR
tRSR
tRSR
tRSR
tRSS RSDR(2) tRSS RT tRSS SEN tRSS SREN tRSF EF/OR tRSF FF/IR tRSF PAE tRSF PAF tRSF Q0 - Qn
tRSR
If FWFT = HIGH, OR = HIGH If FWFT = LOW, EF = LOW If FWFT = LOW, FF = HIGH If FWFT = HIGH, IR = LOW
OE = HIGH OE = LOW
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NOTES: 1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset is complete. 2. The status of these pins are latched in when the Master Reset pulse is LOW.
Figure 8. Master Reset Timing
29
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PRS tRSS REN tRSS WEN tRSS RT tRSS SEN tRSS SREN
tRS tRSR
tRSR
tRSF EF/OR tRSF FF/IR tRSF PAE tRSF PAF tRSF Q0 - Qn
If FWFT = HIGH, OR = HIGH If FWFT = LOW, EF = LOW If FWFT = LOW, FF = HIGH If FWFT = HIGH, IR = LOW
OE = HIGH OE = LOW
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NOTE: 1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset is complete.
Figure 9. Partial Reset Timing
30
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
NO WRITE
tCLKH1
2
tCLK1 tCLKL1 tDH DX tSKEW1
(1)
NO WRITE
WCLK D0 - D39
tSKEW1
(1)
1
tDS
1
2
tDS DX+1 tWFF
tDH
tWFF FF
tWFF
tWFF
WEN RCLK tENS REN tENS RCS tA Q0 - Q39 tRCSLZ
DATA READ
tENH
tENS
tENH
tA
NEXT DATA READ
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NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle. 2. OE = LOW, EF = HIGH. 3. WCS = LOW. 4. WCLK must be free running for FF to update.
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)
31
NO WRITE
tCLK2 tCLKH2 tCLKL2
1 2 2
NO WRITE
WCLK
1
tSKEW2(1) tDS tDH
Dx Dx+1 Dx+2 Dx+3
tDS tDH
tSKEW2(1)
D0-D39 tWFF tWFF tWFF tWFF
FF
WEN
RCLK tENS tENH
tENS
tENH
REN tA
Next Data Read Next Data
tA
tA
tA
Next Data Read
5995 drw14
Q0-Q39
Data in Output Register
Data Read
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
32
NOTES: 1. tSKEW2 is the minimum time between a falling RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the falling edge of the RCLK and the rising edge of WCLK is less than tSKEW2, then FF deassertion may be delayed one extra WCLK cycle. 2. OE = LOW, EF = HIGH. 3. WCS = LOW, RCS = LOW, WSDR = HIGH and RSDR = HIGH. 4. WCLK must be free running for FF to update.
Figure 11. Write Cycle and Full Flag Timing in Double Data Rate Mode (IDT Standard Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLKH1
tCLK1
tCLKL1 tENS tENH tENS tENH
RCLK
tENS tENH
1
2
REN
tREF
NO OPERATION
NO OPERATION
tREF tA LAST WORD LAST WORD tOHZ
(1)
tREF
EF
tA tA D0 D1
Q0 - Q39
tOLZ tOE
tOLZ
OE
tSKEW1
WCLK
tENS tENH tENS tENH
WEN
tWCSS tWCS
H
WCS
tDS tDH tDS D1
tDH
D0 - D39
D0
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NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle. 2. First data word latency = tSKEW1 + 1*TRCLK + tREF. 3. RCS is LOW. 4. RCLK must be free running for EF to update.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
33
tCLK2
NO Read NO Read NO Read
tCLKH2
NO Read
tCLKL2
RCLK
1 2
tREF
tSKEW2 tREF tREF
(1)
EF tA tA
Dn Dn D0
tA tA
Dn-1
Q0-Q39 tOHZ tOLZ
D1
tOLZ
OE
tOE
WCLK tENS tENH
WEN tWCSS tDH tDH
D1 D0
tWCSH tDS
WCS tDS
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
34
D0-D39
5995 drw16
NOTES: 1. tSKEW2 is the minimum time between a falling WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the falling edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF deassertion may be delayed one extra RCLK cycle. 2. REN = LOW. 3. First data word latency = tSKEW1 + 1*tRCLK + tREF. 4. RCS = LOW, WSDR = HIGH and RSDR = HIGH. 5. RCLK must be free running for EF to update.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 13. Read Cycle, Output Enable, Empty Flag and First Data Word Latency in Double Data Rate Mode (IDT Standard Mode)
RCLK tENS tENH
1
2
tSKEW2(1)
REN tREF tREF
EF tA
W0 W1 W2 W3 W4 W5 W6
tA
tA tA
tA
tA
tA
tA
W7
Q0-Q9
Previous Data in Ouput Register
WCLK
tENS
tENH
WEN
tWCSS
twcSH
WCS tDH
tDS
tDH
tDS
D0-D39
W0 - W3
W4 - W7 5995 drw17
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
NOTES: 1. tSKEW2 is the minimum time between a falling WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the falling edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF deassertion may be delayed one extra RCLK cycle. 2. REN = LOW. 3. First data word latency = tSKEW1 + 1*tRCLK + tREF. 4. RCS = LOW, WSDR = HIGH and RSDR = HIGH. 5. RCLK must be free running for EF to update.
35
Figure 14. Read Cycle, Empty Flag and First Data Word Latency in x40DDR to x10SDR with Bus-Matching and Rate-Matching (IDT Standard Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLK2
NO Read
tCLKH2 tCLKL2
1 2
RCLK tENH tSKEW(1) tENS tENH
tENS
REN tREF tREF tREF
EF tA
Last Word Last 40-bit Word
tA
tA
tA
W0-W1 W2-W3
Q0-Q39
Previous Data
WCLK tENH
WEN tDS
W1 W2 W3
5995 drw18
tDS
tDH tDS tDS
tDH
tDH
tDH
D0-D19
W0
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
36
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle. 2. OE = LOW. 3. First data word latency = tSKEW1 + 1*tRCLK + tREF. 4. RCS = LOW, WCS = LOW, WSDR = LOW and RSDR = HIGH. 5. RCLK must be free running for EF to update.
Figure 15. Read Cycle and Empty Flag in x20SDR to x40DDR with Bus-Matching and Rate-Matching (IDT Standard Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLK2
NO WRITE
tCLKH2 tCLKL2 NO WRITE 1 2 tDS Wx+2 tWFF tWFF Wx+3 tDH tDS tDH tDS Wx Wx+1 tWFF tWFF tDH tDS tDH tSKEW1(1) 2
WCLK 1
tSKEW1(1)
D0-D19
FF
WEN
RCLK tENS tENH
tENS
tENH
REN
tENS
RCS tA DATA READ tA NEXT DATA READ
5995 drw19
Q0-Q39
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
37
tRCSLZ
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle. 2. LD = HIGH, OE = LOW, EF = HIGH. 3. WCS = LOW. 4. WCLK must be free running for FF to update.
Figure 16. Write Cycle and Full Flag Timing in x20DDR to x40SDR with Bus-Matching and Rate-Matching (IDT Standard Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
NO WRITE 1 tDS tDS tDS Wx+2 tWFF Wx+3 tWFF tDH tDS tDH Wx+1 tWFF tDH Wx tWFF tDH tSKEW2(1) 2 1 2
tCLKH1
NO WRITE
tCLK1 tCLKH1
WCLK
tSKEW2(1)
D0-D39
FF
WEN
RCLK tENS tENH
tENS
tENH
REN tENS tA tA
DATA READ
tENS
RCS
tA
tA DATA READ
NEXT DATA READ
tRCSHZ NEXT DATA READ
5995 drw20
Q0-Q19
tRCSLZ
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
38
NOTES: 1. tSKEW2 is the minimum time between a falling RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the falling edge of the RCLK and the rising edge of WCLK is less than tSKEW2, then FF deassertion may be delayed one extra WCLK cycle. 2. OE = LOW, EF = HIGH. 3. WCS = LOW, RCS = LOW, WSDR = HIGH and RSDR = HIGH. 4. WCLK must be free running for FF to update.
Figure 17. Write Cycle and Full Flag in x40SDR to x20DDR with Bus-Matching and Rate-Matching (IDT Standard Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2
RCLK
tENS
REN
tENS tENH tENS tENS tREF
RCS
tREF tRCSHZ LAST DATA tSKEW1(1)
EF
tRCSLZ tA LAST DATA-1 tRCSHZ tRCSLZ tA
Q0 - Qn
WCLK
tENS tENH
WEN
tDS tDH Dx
5995 drw21
Dn
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle. 2. First data word latency = tSKEW1 + 1*TRCLK + tREF. 3. OE is LOW. 4. RCLK must be free running for EF to update.
Figure 18. Read Cycle and Read Chip Select (IDT Standard Mode)
39
WCLK
1
WEN tDS W3 W4 W[D-m-2] tSKEW2 (2)
2 3 1 2
tENS tDS W[n +2] W[n+3] W[n+4] W[D-m-1] W[D-m] W[D-m+1] W[D-m+2] W[D-1] W[
D-1 +1 2
tDS
tDH
tDS W[ W[
D-1 +2 2
tENH WD
D0 - Dn
W1
W2
]
] ]
D-1 +3 2
tSKEW1(1)
RCLK
1
RCS
tENS
REN tRCSLZ tA W1 tREF
Q0 - Qn
PREVIOUS DATA IN OUTPUT REGISTER
OR
PAE
tPAES
tPAFS
PAF tWFF
5995 drw22
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
40
IR
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 3. OE = LOW 4. n = PAE offset, m = PAF offset and D = maximum FIFO depth. 5. D = 16,385 for IDT72T4088, 32,769 for IDT72T4098, 65,537 for IDT72T40108, 131,073 for IDT72T40118. 6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 19. Write Timing (FWFT Mode)
WCLK 2 tSKEW2
(2)
tENS
tENH
1 (1) tSKEW1
WEN
tDS
tDH
D0 - Dn
WD
RCLK
1
tENS
tENS
REN
OE tA tA tA W3 Wm+2
2 2
tOHZ tA W[m+4] W[D-n-1] W[D-n] W[D-1] W[ W[D-n+1] W[D-n+2]
D-1 + 1
tOE tA
D-1 + 2
tA WD tREF
Q0 - Qn W2 W[m+3]
W1
W1
]
W[
]
OR tPAES
PAE
tPAFS
PAF tWFF
tWFF
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
41
IR
5995 drw23
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 3. OE = LOW 4. n = PAE offset, m = PAF offset and D = maximum FIFO depth. 5. D = 16,385 for IDT72T4088, 32,769 for IDT72T4098, 65,537 for IDT72T40108, 131,073 for IDT72T40118. 6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 20. Read Timing (FWFT Mode)
WCLK
2 tSKEW2
(2)
tENS
tENH
1 (1) tSKEW1
WEN
tDS
tDH
D0 - Dn
WD
RCLK
1
tENS
tENS
REN
tENS
tENH
RCS
tRCSLZ tA tA W3 W[D-1] Wm+2 W[m+3] W[m+4] W[D-n-1] W[D-n+1] W[D-n+2] W[D-n] W [ D-1 + 1] 2 W [ D-1 + 2] 2 tA tA W2 tA WD tREF
tRCSHZ
Q0 - Qn
W1
OR
tPAES
PAE
tPAFS
PAF
tWFF
tWFF
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
42
IR
5995 drw24
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle. 2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle. 3. n = PAE Offset, m = PAF offset and D = maximum FIFO depth. 4. D = 16,385 for IDT72T4088, 32,769 for IDT72T4098, 65,537 for IDT72T40108, 131,073 for IDT72T40118. 5. OE = LOW. 6. RCLK must be free running for EF to update.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 21. Read Cycle and Read Chip Select Timing (FWFT Mode)
RCLK
1 2 3
tENS
tENH
tENS
REN tENS tENS tENH tENS
RCS tREF tREF
OR tRCSLZ tA
W1 W2
tRCSHZ
tRCSLZ
W2
5995 drw25
HIGH-Z
Qn
1st Word falls through to O/P register on this cycle
tSKEW
WCLK tENH
tENS
WEN tDS
W2
tDS
tDH
tDH
Dn
W1
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
43
NOTES: 1. It is very important that the REN be held HIGH for at least one cycle after RCS has gone LOW. If REN goes LOW on the same cycle as RCS or earlier, then Word, W1 will be lost, Word, W2 will be read on the output when the bus goes to LOW-Z. 2. The 1st Word will fall through to the output register regardless of REN and RCS. However, subsequent reads require that both REN and RCS be active, LOW. 3. RCS functions similarly to OE, when RCS is HIGH the read pointer will not increment.
Figure 22 . RCS and REN Read Operation (FWFT Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLK2 tCLKH2 1 2 tENS tENS tCLKL2
RCLK
REN tA tA tA
WMK+n WMK WMK+3 WMK+4 WMK+5 WMK+6
tA tA tA tA tA
WMK+2
tA
WMK+1
tA
WMK+2
Q0-Qn
WMK
WMK+1
tENS
tENH
MARK tENS tENH
RT tREF tREF
EF tPAES(7)
PAE tSKEW2 1 2 tPAFS
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
44
WCLK
PAF
5995 drw26
NOTES: 1. Retransmit setup is complete when EF returns HIGH. 2. OE = LOW;RCS = LOW. 3. RT must be HIGH when reading from FIFO. 4. Once MARK is set, the write pointer will not increment past the `marked' location, preventing overwrites of Retransmit data. 5. Before a "MARK" can be set there must be at least 160 bytes of data between the Write Pointer and Read Pointer locations. (160 bytes = 16 words = 8 long words). 6. RCLK must be free running for EF to update. 7. A transition in the PAE flag may not occur until one RCLK cycle later than shown. 8. In DDR mode the MARK function will "MARK" words only on even word boundaries (i.e. Rising edge of RCLK).
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 23 . Retransmit from MARK in Double Data Rate Mode (IDT Standard Mode)
RCLK
1 2
tENS tENS
tENS
REN tA tA tA WMK WMK+1 WMK+1 WMK+n tENH tENS tENH tA tA WMK tENS tA WMK+2
tA
Qn
WMK-1
MARK
RT tREF tREF
OR tPAES(7)
PAE tSKEW2
1 2
WCLK tENS
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
45
WEN tPAFS
PAF
5995 drw27
NOTES: 1. Retransmit setup is complete when OR returns LOW. 2. OE = LOW;RCS = LOW. 3. RT must be HIGH when reading from FIFO. 4. Once MARK is set, the write pointer will not increment past the `marked' location, preventing overwrites of Retransmit data. 5. Before a "MARK" can be set there must be at least 160 bytes of data between the Write Pointer and Read Pointer locations. (160 bytes = 16 words = 8 long words). 6. RCLK must be free running for EF to update. 7. A transition in the PAE flag may not occur until one RCLK cycle later than shown.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 24. Retransmit from Mark (FWFT Mode)
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
tSCLK tSCKL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tSCKH
SCLK
tSENS tSENH tENH
SEN
tSDS tSDH
BIT 1 EMPTY OFFSET BIT X
(1)
SI
BIT 1
FULL OFFSET
BIT X
(1)
5995 drw28
NOTE: 1. In SDR mode, X = 14 for the IDT72T4088, X = 15 for the IDT72T4098, X = 16 for the IDT72T40108, X = 17 for the IDT72T40118. 2. In DDR mode, X = 13 for the IDT72T4088, X = 14 for the IDT72T4098, X = 15 for the IDT72T70108, X = 16 for the IDT72T40118.
Figure 25. Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tSCKH
tSCLK tSCKL
SCLK
tSENS tSENH tENH
SREN
tSOA tSOA
BIT 0
SO
BIT X EMPTY OFFSET
(1)
BIT 0
FULL OFFSET
BIT X
(1)
5995 drw29
NOTE: 1. In SDR mode, X = 14 for the IDT72T4088, X = 15 for the IDT72T4098, X = 16 for the IDT72T40108, X = 17 for the IDT72T40118. 2. In DDR mode, X = 13 for the IDT72T4088, X = 14 for the IDT72T4098, X = 15 for the IDT72T40108, X = 16 for the IDT72T40118. 3. Offset register values are always read starting from the first location in the offset register upon initiating SREN.
Figure 26. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes)
46
NO Read
NO Read
RCLK
tERCLK
ERCLK tENH tENS
REN tENH tCLKEN tCLKEN tCLKEN tCLKEN tENS tCLKEN
tENS
RCS
tCLKEN
EREN tREF tA tA tOLZ
WD-9 WD-3 WD-8 WD-7 WD-6 WD-6 WD-5 WD-4
EF tA
tA
tOLZ
tA
tA
tA tA
WD-2
tOLZ
tA
tA
WD-1 Last Word WD
5995 drw30
Qn
WD-10
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
47
EREN 0 1 1 1 1
NOTES: 1. The EREN output is "or gated" to RCS and REN and will follow these inputs provided that the FIFO is not empty. If the FIFO is empty, EREN will go HIGH to indicate that there is no new word available. 2. The EREN output is synchronous to RCLK. 3. OE = LOW. 4. The truth table for EREN is shown below:
RCLK
EF
RCS
REN

1 1 1 1 0
0 0 1 1 X
0 1 0 1 X
Figure 27. Echo Read Clock & Read Enable Operation in Double Data Rate Mode (IDT Standard Mode Only)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
WCLK tENS WEN tDS D0 - Dn tDH tDS tDH tDS tDH tENH
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Wn+1
Wn+2 tSKEW1
1
Wn+3
2 b c d e f g h i
RCLK tERCLK ERCLK
a
REN tENS RCS tCLKEN EREN tCLKEN
tENS
tENH
tCLKEN
tCLKEN
tRCSLZ Qn
HIGH-Z
tA Wn+2
tA Wn+3 tREF
Wn+1 tREF
OR tA O/P Reg. Wn Last Word Wn+1 tA Wn+2 tA Wn+3
5995 drw31
NOTE: 1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in HighImpedance state. 2. OE is LOW. Cycle: a&b. At this point the FIFO is empty, OR is HIGH. RCS and REN are both disabled, the output bus is High-Impedance. c. Word Wn+1 falls through to the output register, OR goes active, LOW. RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register. d. EREN goes HIGH, no new word has been placed on the output register on this cycle. e. No Operation. f. RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available. NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made available for at least one cycle. g. REN goes active LOW, this reads out the second word, Wn+2. EREN goes active LOW to indicate a new word has been placed into the output register. h. Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out. NOTE: Wn+3 is the last word in the FIFO. i. This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available. 3. OE is LOW. 4. The truth table for EREN is shown below: RCLK OR 0 0 0 0 1 RCS 0 0 1 1 X REN 0 1 0 1 X EREN 0 1 1 1 1
Figure 28. Echo RCLK and Echo REN Operation (FWFT Mode Only)
48
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
tCLKL1 tCLKH1 1 tENS tENH 2 1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
WCLK WEN
2
tPAFS
tPAFS
D - m words in FIFO
(2)
PAF
D - (m +1) words in FIFO
(2)
D-(m+1) words (2) in FIFO
tSKEW3
(3)
RCLK
tENS tENH
5995 drw32
REN
NOTES: 1. m = PAF offset. 2. D = maximum FIFO Depth. In IDT Standard Mode: D=16,384 for the IDT72T4088, 32,768 for the IDT72T4098, 65,536 for the IDT72T40108, 131,072 for the IDT72T40118. In FWFT Mode: D=16,385 for the IDT72T4088, 32,769 for the IDT72T4098, 65,537 for the IDT72T40108, 131,073 for the IDT72T40118. 3. PAF is asserted and updated on the rising edge of WCLK only. 4. tSKEW3 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW3, then the PAF deassertion time may be delayed one extra WCLK cycle. 5. RCS = LOW.
Figure 29. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH1
tCLKL1
WCLK
tENS tENH
WEN PAE
n words in FIFO , (3) n + 1 words in FIFO
(2)
tSKEW3
(4)
tPAES 2 tENS
n + 1 words in FIFO , (3) n + 2 words in FIFO
(2)
n words in FIFO , (3) n + 1 words in FIFO
(2)
tPAES 1 2
RCLK REN
1
tENH
5995 drw33
NOTES: 1. n = PAE offset. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. PAE is asserted and updated on the rising edge of RCLK only. 5. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then the PAE deassertion may be delayed one extra RCLK cycle. 5. PAE is asserted and updated on the rising edge of RCLK only. 6. RCS = LOW.
Figure 30. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
49
IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the EF and FF functions in IDT Standard mode and the IR and OR functions in FWFT mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 31 demonstrates a width expansion using two IDT72T4088/ 72T4098/72T40108/72T40118 devices. D0 - D40 from each device form a 80bit wide input bus and Q0-Q39 from each device form a 80-bit wide output bus. Any word width can be attained by adding additional IDT72T4088/72T4098/ 72T40108/72T40118 devices.
SERIAL CLOCK (SCLK) PARTIAL RESET (PRS) MASTER RESET (MRS) FIRST WORD FALL THROUGH (FWFT) RETRANSMIT (RT) Dm+1 - Dn m+n DATA IN D0 - Dm
m
n
READ CLOCK (RCLK) READ CHIP SELECT (RCS) READ ENABLE (REN) IDT 72T4088 72T4098 72T40108 72T40118 IDT 72T4088 72T4098 72T40108 72T40118
WRITE CLOCK (WCLK) WRITE ENABLE (WEN)
OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG/OUTPUT READY (EF/OR) #1
FULL FLAG/INPUT READY (FF/IR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2 PROGRAMMABLE (PAF) FIFO #1 FIFO #2
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
GATE
n
Q - Qn m+1
m+n DATA OUT
m
Q0 - Qm
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NOTES: 1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode. 2. Do not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 31. Block Diagram of 16,384 x 80, 32,768 x 80, 65,536 x 80, 131,072 x 80 Width Expansion
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IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSyncTM DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40
FWFT TRANSFER CLOCK WRITE CLOCK WRITE ENABLE INPUT READY FWFT WCLK WEN IR RCLK
WCLK WEN IR
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FWFT
RCLK
READ CLOCK READ CHIP SELECT READ ENABLE OUTPUT READY OUTPUT ENABLE n DATA OUT
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IDT 72T4088 72T4098 72T40108 72T40118
OR REN RCS OE GND n
IDT 72T4088 72T4098 72T40108 72T40118
RCS REN OR OE
DATA IN
n Dn Qn
Dn
Qn
Figure 32. Block Diagram of 32,768 x 40, 65,536 x 40, 131,072 x 40, 262,144 x 40 Depth Expansion in Single Data Rate Mode
DEPTH EXPANSION CONFIGURATION IN SINGLE DATA RATE (FWFT MODE ONLY) The IDT72T4088 can easily be adapted to applications requiring depths greater than 16,384, 32,768 for the IDT72T4098, 65,536 for the IDT72T40108, 131,072 for the IDT72T40118 with an 40-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 32 shows a depth expansion using two IDT72T4088/72T4098/72T40108/72T40118 devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. Also, the devices must be operating in Single Data Rate mode since that is the only mode available in FWFT. The first word written to an empty configuration will pass from one FIFO to the next ("ripple down") until it finally appears at the outputs of the last FIFO in the chain - no read operation is necessary but the RCLK of each FIFO must be free-running. Each time the data word appears at the outputs of one FIFO, that device's OR line goes LOW, enabling a write to the next FIFO in line. For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR flag. The "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. There will be no delay evident for subsequent words written to the configuration. The first free location created by reading from a full depth expansion configuration will "bubble up" from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO to write a word to fill it. For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: (N - 1)*(3*transfer clock) + 2 TWCLK where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR flag. The Transfer Clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.
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ORDERING INFORMATION
IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK I(1) BB 4 5 6-7 10 L 72T4088 72T4098 72T40108 72T40118 Commercial (0C to +70C) Industrial (-40C to +85C) Plastic Ball Grid Array (PBGA, BB208-1) Commercial Only Commercial Only Commercial and Industrial Commercial Only Low Power 16,384 x 40 32,768 x 40 65,536 x 40 131,072 x 40 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 2.5V High-Speed TeraSyncTM DDR/SDR FIFO 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
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Clock Cycle Time (tCLK) Speed in Nanoseconds
NOTE: 1. Industrial temperature range product is available for 6-7ns as a standard product. All other speed grades are available by special order.
DATASHEET DOCUMENT HISTORY
03/01/2002 04/08/2002 04/24/2002 05/24/2002 11/21/2002 02/11/2003 03/20/2003 12/17/2003 pgs. pgs. pgs. pgs. pgs. pgs. pgs. pgs. 1, 4, 6, 8, 9, and 23. 1, 8, 9, 11, 33-37, 42, 46-48, and 51. 19, and 28. 6-9, and 12. 1, and 10. 7, 8, and 27. 25, 27, 28, and 44. 10, 31-34, 36-38, 44, and 49. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: 408-330-1753 email: FIFOhelp@idt.com

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